Serial I/O Links

The strong increase in bandwidth for data communication mainly due to the growth of the internet data traffic, demands an increase in data throughput in chip-to-chip and system-to-system links as well. Electrical backplane interconnects up to 1m at 10 Gbps are feasible at a large power consumption. However, the relatively large power consumption of electrical interconnects limits the number of links per chip, as the maximum chip power is in the order of 100 W. As a consequence, optical technology is required for Tbps data throughput and link distances >1m. The goal is to investigate key circuit blocks for electrical and optical interconnects.

Project: High Speed Communication Receiver in CMOS for 40 Gb/s Serial Optical Link

The goal of this project is a receiver including a dual-loop clock and data recovery (CDR) circuit. The project HIGHSCORE (High Speed Communication Receiver in CMOS for 40 Gb/s Serial Optical Link) is funded by KTI (Project 6726.1 FHS).

Project Partners:

• Institut für Mikroelektronik, Fachhochschule Nordwestschweiz (Project Managment of HIGHSCORE)
• I/O Link Technology group at IBM Research Laboratory, Rüschlikon
• Bern University of Applied Sciences

Research Scientists: Lucio Rodoni, George von Büren

Project: Ultra-fast CMOS Transceiver Design for Optical Interconnect Applications

The goal of this project was to demonstrate a CMOS transceiver for short-range fiber optical interconnects. The project VISION is funded by KTI (Project KTI Nr. 4900.1).

Project Partners:

• High-Speed Interconnect Technology Group at IBM Research Laboratory, Rüschlikon

Research Scientists: Christian Kromer (now with Aprius Inc.), Gion Sialm (now with Sialm EC)

Highlights

• Industry Day ETH Zurich September 4, 2006: (doc; poster)
• Article in german in "Technische Rundschau 17/2005": Version Small, Version Big